Delay device

ABSTRACT

A capacitive delay device comprising a sequence of capacitances which have been interconnected by the main current path of at least one transistor, a feedback path being provided between the output electrode of at least one transistor and the input electrode thereof.

United States Patent Sangster 1 May 30, 1972 54] DELAY DEVICE [56] References Cited [72] Inventor: Frederik L- J. Sangster, Emmasingel, UNITED STATES PATENTS Eindhoven, Netherlands 3,395,292 7/1968 Bogert ..307/304 X [73] Assignee: U.S. Philips Corporation, New York, N.Y. 3 431 433 3 19 9 Ba" ct 1 un 22 3 474 260 10/1969 Frohbach ..307/221 N 2 1970 [22] Wed 1 3,546,490 12/1970 Sangster ..307/246 x [21] Appl. No.2 88,742

Primary Examiner-Stanley D. Miller, Jr. [30] Foreign Application Priority Data Atmmey Frank Tnfan Sept. 25. 1970 Netherlands ..70|4135 ABSTRACT A capacitive delay device comprising a sequence of [52] U.S.Cl. ..307/293, 307/221 C, 307/246, capacitances which have been interconnected by the: main 307/304 current path of at least one transistor, a feedback path being [51] Int. Cl. ..H03k17/26 provided between the output electrode at least one [58] Field of Search ..307/221 R, 221 C, 246, 293,

transistor and the input electrode thereof.

Patented May 30, 1972 3 Sheets-Sheet 1 INVENTOR.

FREDERI K L.J. SANGSTER AGENT DELAY DEVICE The invention relates to a device for delaying a train of signal samples of an electrical signal. The device comprises a sequence of stages which each include a first and a second capacitance interconnected by means of the main current path of at least one transistor. The second capacitance of each stage forms the first capacitance of the succeeding stage, while the input electrode circuit of the transistor includes the first capacitance and its output electrode circuit includes the second capacitance. A switching voltage source is arranged to be connected between the control electrode of the transistor and that terminal of the first capacitance which is not connected to the input electrode of the transistor. In a known arrangement of this kind, as described in Netherlands Patent application No. 6,805,705, corresponding to US. Pat. application, Ser. No. 817,690, filed Apr. 21, 1969 and now abandoned the transistor is a field efi'ect transistor. The field efi'ect transistors are interconnected in groups so as to form junction points to which switching signals are applied which are ascendingly shifted in phase in the order of the numbers of the junction points.

Applicant recognizes the problem that when a large number of stages was used satisfactory operation was interfered with by the fact that in each stage a slight degradation of sudden voltage variations occurs. This means that when the input voltage abruptly changes from volts to Vvolts, the output signal at the output of the arrangement changes from 0 volts to (V& volts, where 8 is the error voltage. If subsequently the input signal remains at the value of V volts, the output signalwill also assume this value. The said effect deleteriously afiects the frequency characteristic of the device.

It is an object of the present invention to provide a solution of the said problem, and a device according to the invention is characterized in that feedback is provided between the output electrode of the transistor of at least one of the stages and the input electrode circuit of the said stage, by which feedback during the transfer of information between the first and the second capacitances of the said stage there is produced in series with the input electrode circuit a voltage which is a fraction of the voltage set up at the output electrode of the transistor and which has the same polarity as the threshold voltage of the transistor in the conductive condition thereof.

The invention is based on the recognition that the said signal degradation is due to the fact that the threshold voltage of a transistor depends on the transferred signal value AV. When a comparatively small number of stages is used, this effect will not be troublesome, but when a large number of stages, for example several hundreds of stages, are used, it will be highly troublesome. The effect will be particularly strong when the transistors used are field effect transistors. This is due to the fact that electrostatic reaction takes place from the drain electrode by way of the substrate on the boundary region between the source electrode and the drain electrode of the field effect transistor used, and that on the other hand the length of the depletion layer slightly depends on the voltage at the drain electrode. In field effect transistors having a high-resistivity substrate the electrostatic reaction is the dominant factor, whereas in field effect transistors having a low-resistivity substrate the second effect is dominant.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which:

FIG. 1 shows the known arrangement,

FIG. 2 shows the voltage waveforms at different points in the known arrangement,

FIG. 3 shows an embodiment of an arrangement according to the invention and FIG. 4 shows the voltage waveforms at various points in the arrangement of FIG. 3.

In the known delay device shown in FIG. 1, the main current paths of field efi'ect transistors T,,, T,, T T,, are connected in series. A capacitor C has been connected between the drain and the gate of the transistor T,,. A capacitor C, has

been connected between the drain and the gate of the transistor T,. A capacitor C, has been connected between the drain and the gate of the transistor T,. A capacitor C, has been connected between the drain and the gate of the transistor T,,. The gate of the transistor T, has been connected to an output 8, of a switching voltage source S The gates of the transistors T and T, have .been connected to an output S, of the switching voltage source S A diode D,, has one terminal connected to the drain of the transistor T,, and the other tenninal connected to the output 8, of the switching voltage source S,,. The source of the transistor T,, has been connected to a point of constant potential through the series combination of a resistor T,,, an input voltage source V, and a direct-voltage source E,.

The operation of the known arrangement will be described with reference to FIG. 2. FIGS. 2b and 2c show the voltage waveforms at the outputs S and 8,, respectively. These voltages are symmetrical square-wave voltages having a maximum of 0 volt and a minimum of E volts. During the time in which the voltage at the points S, is negative with respect to earth, i.e. during time intervals 1 1-,, 1,, 1 etc. in FIG. 2b, information about the value of the input signal V, is transferred to the capacitor C During the time interval 1', the input signal V, is small, see FIG. 2a, whereas during the time interval 1-, and the following time intervals the input signal V, is large. During the time interval r there will flow through the transistor T,, a current of about V,/R,, amperes, where V, is the value of the input signal during the time interval 1', under consideration and R is the resistance of the resistor R of FIG. 1. The said current will cause the voltage at the drain of the transistor T to increase by an amount AV,, see FIG. 2d. During the time interval 1-,, the capacitor C is discharged through the transistor T, until the voltage across this capacitor has become equal to (EV,,) volts, where V is the threshold voltage of the transistor T,, the value of this threshold voltage being determined by the signal value AV,. During the time interval 1-, charge is again supplied to the capacitor C through the transistor T,,, so'that the voltage at the drain of the transistor T,, will rise by an amount of AV,. volts, see FIG. 2d. During the time interval 1-,, the capacitor C is discharged through the transistor T, until the voltage across this capacitor has become equal to (E V,,) volts, where V',, is that threshold voltage of the" transistor T, which is associated with the signal value AV,.. It has been found that the threshold voltage V',, associated with the signal value AV,. exceeds the threshold voltage V, associated with the signal value AV, by an amount of 8 volts. This means that the voltage drop across the capacitor C which occurs during the time interval 7, will be equal to (AVf'S) volts instead of to AV, volts. At the instant at which the time interval 7,, begins the voltage at the drain of the transistor T will be equal to 2E V.,)+} volts, see FIG. 2d. At the end of the said time interval the voltage at the drain of the transistor T0 will be equal to {(2EV,,H-8+AV-,} volts. Consequently, the voltage drop across the capacitor C will be equal to AV volts during this time interval.

During the time interval 1-,, the capacitor C, is charged through the transistor T, until the voltage across this capacitor has risen by an amount of AV, volts, see FIG. 2e. During the time interval 7, the capacitor C, is discharged through the transistor T, until the voltage across this capacitor has become equal to -(EV,,) volts, where V, is the threshold voltage of the transistor T associated with the signal value AV,. During the time interval 7 the capacitor C, is charged through the transistor T,. The voltage rise across the capacitor C, will be equal to the voltage drop across the capacitor C,, during the time interval under consideration. Consequently, the said voltage rise will be equal to (AV 6) volts. During the time interval 1-,, the capacitor C, is discharged through the transistor T until the voltage across this capacitor has become equal to (E V.,) volts, where V 1 isthe threshold voltageof the transistor T associated with the signal value (AV 6). Since 8 is much smaller than AV we have to a good approximation: V",,=V',,. This means that the voltage drop across the capacitot C, during the time interval 1', will be equal to (AV,2 6) volts instead of to AV, volts, as it should have been. A simple calculation shows that the voltage drop across the capacitor C,, of the capacitive store of FIG. 1, which voltage drop corresponds to the voltage drop (AV,6) volts across the capacitor C, during the time interval 1-,, will be equal to (AV,-n. 6) volts, where n is the number of the capacitor C,,. However, this will hold only if n. A is small compared with AV,. If n. 8 becomes comparable to AV,, Le. if n is large, the corresponding voltage drop will be equal to (l- 6)" volts. However, if n. 8 becomes comparable to the signal value AV,, second-order and third-order efi'ects also will occur. This means that in contradistinction to the example discussed with reference to FIGS. 24 and 2c in which one signal value only was not correct .(see the interval r, of FIG. 2d and the interval 'r, of FIG. 2e), at least two successive signal values will not be correct, as is shown diagrammatically in FIG. 2f. In this Figure the signal values during the intervals -r,,, and 1-, are not correct. During the interval 7,, the signal value is equal to (AV,6,,) volts, and during the interval 1 it is equal to (AV,6,,) volts. Not before the interval 1-,, will the signal value be correct and equal to AV, volts. 7 FIG. 3shows a delaydevice according to the invention. It comprises transistors T T,, T, and "I1, the main current paths of which have been connected in series. Capacitors C C,, C, and C have been connected between the drain and gate electrodes of the transistors T T T, and T,,.,,, respectively; The source of the transistor T, has been connected to a point of constant potential through the series combination of a resistor R and a signal voltage source V,. The gate of the transistor T has been connected to an output S, of a;switching voltage source S and the gates of the transistors T and T have been connected to an output S, of the switching voltage source S The gate of the transistor T,, has been connected to the output S of the switching voltage source 8,, through a resistor R,. The drain of the transistor T has beenconnected, through adiode D, to the output S, of the switching voltage source 5,, and also, through a follower circuit F and a resistor R "to the gate of the transistor T,,. The operation of the delay device of FIG. 3 will be described with reference to FIG. 4. v

' F IGS. 4a and 41: show the voltage waveforms at the outputs S, and S, of the switching voltage source. FIG. 40 shows the voltage at a point B, of the delay device'and FIGS. 4d and 4e show the charges present in the capacitors C, and C, respectively as functions of time. During the time interval 1-,, information from acapacitor preceding the capacitor C,, is transferred to the capacitor C,, It is assumed that during this interval no charge is transferred to the capacitor C,, This means that the final charge in this capacitor is equal to +C(E V coulombs, where C is the capacitance of the capacitors C,,..,, C, and C,, It is further assumed that during the same time interval no charge is transferred between the capacitors C, and C,, This means that during the said interval the voltage at the point B, will be equal to 2p (Li-V volts, where p is equal to the quotient (R,/R,+R,). This means that during the said interval the charge in the capacitor C,, will be equal to Q, (0) C( l2p) (IE-V coulombs (1) During the time interval 7, no charge is transferred between the capacitor C,, and the capacitor C,,, since during this interval the transistor T, will not be conductive. This means that the charge Q,, (1) will be equal to the charge Q, (0), see FIG.

4d. lt is assumed that during the time interval 1', a charge equal to la). AV C is transferred to the capacitor C,, where a is an attenuation factor and AV is the value of the signal sample asinitially applied to the input of the delay device. During the same time interval no charge transfer takes place between the capacitors C,, and C so that the charge states of these capacitors will remain unchanged, see FIGS. 4d and 4e. During the time interval 1', no charge transfer takes place between the capacitors C,. and.C,,. A charge equal to (1-0) AV- C coulombs is supplied to the capacitor C,,. Hence, the final charge in this capacitor will be equal to i Qn (3) 1-2p) (e-V,,)+( la)AV }coulombs (2) see FIG. 4d. During the time interval 1, a charge transfer takes place between the capacitors C, and C,,.,,. At the beginning of this time interval the charge in the capacitor C is equal to C(EV coulombs, see FIG. 42, whilst the initial charge in the capacitor C,, is given by the relation (2). At the end of the interval under consideration, the voltage across the capacitor C is desired to be equal to (EV,) +AVvolts, since in this event the attenuation involved will be compensated. This will be achieved if a charge equal to C AVcoulombs is transferred from the capacitor C, to the capacitor C,,,.,. Consequently, the final charge in the capacitor C, will be equal to (Q,,(4) C{(l2p)(EV )-l-(1--a)AV-AV} coulombs(3) see FIG. 4d. On the other hand, if the final voltage across the capacitor C is equal to (E.V )+AVvolts, the voltage at the point B, will be equal to 2p (IE-V +p'AVvolts, see FIG. 40. The voltage at the source of the transistor T, will be equal to (E V volts during the charge transfer. Hence the voltage across the capacitor C, will be equal to (1 2p) (E- Va) pAV volts and consequently the charge in the capacitor C will be equal to A closer consideration of the relations (3) and (4) will show that by making p=a the desired compensation for the attenuation is obtainable.

In the delay device shown in FIG. 3, the compensation circuit has been included in the final stage (n+1). For practical reasons it may be desirable for the compensation circuit to be included not in the final stage but in one of the preceding stages. In this case, however, it is desirable to make p a with some consequent overcompensation which will enable the correct frequency characteristic to be obtained at the output of the delay device. When the delay device comprises a large number of stages, several stages may be provided with overcompensation, which additionally achieves an improved signal-to-noise ratio of the delay device. Instead of in series with the capacitor C,, the resistor R, may be connected between the gate of the transistor T and the output S, of the switching voltage source S, with the interposition of an inverter. Further, instead of the resistors R, and R, a capacitor C may be connected between the source of the transistor T, and the source of the transistor T, in which case the source of the transistor T is also connected through a resistor to a point of constant potential. The feedback factor p will in this .case be equal to (C /C), where C is the'capacitance of the capacitor C, and C, is the capacitance of the aforementioned capacitor. Also, the follower circuit shown inFIG. 3 may be replacedby any other follower circuit. In addition, the device shown in FIG. 3 is suitable to be at least partially integrated in v a semiconductor body. i

What is claimed is:

1. A device for delaying a of signal samples of an electrical signal, comprising a plurality of interconnected stages,

each stage comprising a transistor having a control input and a main conduction path comprising a signal input and a signal output, wherein current through the main conduction path is a function of voltage between the control input and'the signal 7 input thereof, each stage further comprising a capacitor and first means for connecting the capacitor across the control input and signal output of the transistor, the device further comprising second means for serially connecting the main conduction paths of the transistors in all of the stages, means connected to the control inputs of the transistors in all of the stages for receiving switching pulses having a magnitude sufficient to render alternate transistors of the device conducting,

and feedback means connecting the signal output of a preceeding the selected stage and the signal input of the transistor in the selected stage, a second resistor connected to the first resistor and the capacitor of the stage proceeding the 3 ,666,972 5 6 selected stage and a non-inverting amplifier having an output electrodes of which form the output and input respectively of connected through the second resistor to the first resistor and the non-inverting amplifier circuit.

an input connected to the signal output of the transistor in the A device as claimed in claim 1, wherein a Substantia pop selected stage.

3. A device as claimed in claim 2, wherein the non-inverting .5 of the devlce ls Integrated m a Semiconductor body amplifier comprises a field effect transistor, the drain and gate 

1. A device for delaying a train of signal samples of an electrical signal, comprising a plurality of interconnected stages, each stage comprising a transistor having a control input and a main conduction path comprising a signal input and a signal output, wherein current through the main conduction path is a function of voltage between the control input and the signal input thereof, each stage further comprising a capacitor and first means for connecting the capacitor across the control input and signal output of the transistor, the device further comprising second means for serially connecting the main conduction paths of the transistors in all of the stages, means connected to the control inputs of the transistors in all of the stages for receiving switching pulses having a magnitude sufficient to render alternate transistors of the device conducting, and feedback means connecting the signal output of a transistor in a selected stage of the device to the signal input of the transistor in the selected stage for feeding a portion of the voltage on the capacitor of the selected stage to the signal input terminal of the associated transistor.
 2. A device as claimed in claim 1, further comprising a first resistor serially connected with the capacitor of a stage preceeding the selected stage and the signal input of the transistor in the selected stage, a second resistor connected to the first resistor and the capacitor of the stage preceeding the selected stage and a non-inverting amplifier having an output connected through the second resistor to the first resistor and an input connected to the signal output of the transistor in the selected stage.
 3. A device as claimed in claim 2, wherein the non-inverting amplifier comprises a field effect transistor, the drain and gate electrodes of which form the output and input respectively of the non-inverting amplifier circuit.
 4. A device as claimed in claim 1, wherein a substantial portion of the device is integrated in a semiconductor body. 